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-- Company: 
-- Engineer:
--
-- Create Date:   22:46:13 01/16/2010
-- Design Name:   
-- Module Name:   C:/Documents and Settings/sxs5464/Desktop/RapidFPGA/code/Xilinx Projects/D3board/demoTB.vhd
-- Project Name:  D3board
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: demo
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY demoTB IS
END demoTB;
 
ARCHITECTURE behavior OF demoTB IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT demo
    PORT(
         FPGA_Clk : IN  std_logic;
         I2C_Clk : OUT  std_logic;
         I2C_Data : IN  std_logic;
         LED : OUT  std_logic_vector(3 downto 0);
         SW : IN  std_logic_vector(3 downto 0);
         IMG_Data : IN  std_logic_vector(9 downto 0);
         IMG_PIXEL_Clk : IN  std_logic;
         IMG_ROW_Clk : IN  std_logic;
         IMG_ROW_Clk_EN : IN  std_logic;
         IMG_VSYNC : IN  std_logic;
         IMG_RST : IN  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal FPGA_Clk : std_logic := '0';
   signal I2C_Data : std_logic := '0';
   signal SW : std_logic_vector(3 downto 0) := (others => '0');
   signal IMG_Data : std_logic_vector(9 downto 0) := (others => '0');
   signal IMG_PIXEL_Clk : std_logic := '0';
   signal IMG_ROW_Clk : std_logic := '0';
   signal IMG_ROW_Clk_EN : std_logic := '0';
   signal IMG_VSYNC : std_logic := '0';
   signal IMG_RST : std_logic := '0';

 	--Outputs
   signal I2C_Clk : std_logic;
   signal LED : std_logic_vector(3 downto 0);
	
	constant clk_period : time:=20 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: demo PORT MAP (
          FPGA_Clk => FPGA_Clk,
          I2C_Clk => I2C_Clk,
          I2C_Data => I2C_Data,
          LED => LED,
          SW => SW,
          IMG_Data => IMG_Data,
          IMG_PIXEL_Clk => IMG_PIXEL_Clk,
          IMG_ROW_Clk => IMG_ROW_Clk,
          IMG_ROW_Clk_EN => IMG_ROW_Clk_EN,
          IMG_VSYNC => IMG_VSYNC,
          IMG_RST => IMG_RST
        );
 
 
   clk_process :process
   begin
		FPGA_Clk <= '0';
		wait for clk_period/2;
		FPGA_Clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100ms.
      wait for 100ms;	

      wait for clk_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;
